1. Field of the Invention
The present invention relates to a flat panel display device, and more particularly, to a data control circuit for a flat panel display device and a flat panel display device having a data control circuit.
2. Description of the Related Art
With the development of various kinds of portable devices such as mobile phones or laptops and information electronic devices for implementing high-resolution, high-quality images such as HDTV, the demand for flat panel display devices for use in these devices is growing. Examples of these flat panel display devices include liquid crystal displays (LCDs), plasma display panels (PDPs), field emission displays (FEDs), and organic light-emitting diodes (OLEDs).
Typically, a flat panel display device includes a plurality of gate lines and a plurality of data lines intersecting the gate lines that are formed on a display panel. A plurality of pixels including thin film transistors, which are driving elements, are formed at the intersections of the two types of lines. Each pixel has an electric current passing through it by a signal applied from the gate lines, and displays an image in response to a signal applied from the data lines.
Therefore, at least one gate line and at least one data line have to be connected to each pixel, at least one data line is allocated to pixels arranged in the same horizontal line, and each data line has to be connected one-to-one to one channel of a data driver that supplies video-related signals.
However, in line with the trend of flat panel display devices with large surface area and high resolution, the number of data lines is increasing. To cope with this, the number of channels of the data driver is also increasing, and the internal logic becomes complicated, leading to an increase in the manufacturing cost of the data driver.
To overcome this problem, there was suggested a structure that enables the data driver to use fewer channels by sharing one channel between two or more second lines.
FIG. 1 is a view schematically showing part of a related art channel-reduced flat panel display device. The following drawing illustrates an application example of a 3×1 multiplexer structure that connects three data lines to a single channel.
As shown therein, the related art channel-reduced flat panel display device includes data lines DL1 to DL6 connected to a plurality of pixels and a MUX driver 50 that connects two channels ch1 and ch2 of the data driver 20.
The MUX driver 50 offers the advantage of reducing the number of channels Chn of the data driver to one-third of the related art one by time-dividing one horizontal period 1H into three parts and selectively connecting the data lines DL1 to DL6 and the channels ch1 and ch2, in response to control signals SMUX1 to SMUX3 applied from a MUX controller (not shown) provided in the outside. For each control signal SMUX1 to SMUX3, one data line DL1 to DL6 and one channel ch1 and ch2 are electrically connected. For example, when the first control signal SMUX1 is applied, the first data line DL1 and the first channel ch1 are connected.
The voltage level of the control signals SMUX1 to SMUX3 for driving the MUX driver 50 has a difference of about 3.0 V from a data voltage applied through the data lines D1 to DL6. For example, according to polarity inversion driving, a positive (+) data voltage ranges from +5.0 V to −5.0 V, and a negative (−) data voltage ranges from 0 V to −5 V. Since the voltage level of the control signals SMUX1 to SMUX3 has a difference of about 3.0 V from the data voltages, as described above, the actual voltage level ranges from about 9.0 V to 9.0 V, with a difference of 1.0 V from the data voltages.
That is, the control signals SMUX1 to SMUX3 are within the range of about +9 V to −9 V, regardless of data polarity, and are applied to the MUX driver 50, with a voltage swing width of 18 V every ⅓ horizontal period.
Accordingly, the power consumed to apply a control signal to the MUX driver 50 having the structure of FIG. 1 can be expressed by the multiplication of the capacitance of control lines to which a control signal is applied, the frequency F of the control signal, the difference Vsupply between the high and low levels of a voltage supplied to the control lines, and the voltage swing Vswing of the control signal.power=C×F×Vsupply×Vswingpower=C×F×324  [Equation 1]
That is, the related art MUX driver 50 has the drawback that the large voltage difference between two neighboring control lines and the large voltage swing can lead to a delay in the rising time and falling time of switching elements constituting the MUX driver 50, thus causing malfunction and high power consumption.